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The 960 architectures provide combined Compare-and-Branch instructions that permit you to store the branch target in the lower 13 bits of the instruction word itself. However, if you specify a branch target far enough away that its address won't fit in 13 bits, the assembler can either issue an error, or convert your Compare-and-Branch instruction into separate instructions to do the compare and the branch.
Whether as
gives an error or expands the instruction depends
on two choices you can make: whether you use the `-no-relax' option,
and whether you use a "Compare and Branch" instruction or a "Compare
and Jump" instruction. The "Jump" instructions are always
expanded if necessary; the "Branch" instructions are expanded when
necessary unless you specify -no-relax
---in which case
as
gives an error instead.
These are the Compare-and-Branch instructions, their "Jump" variants, and the instruction pairs they may expand into:
Compare and Branch Jump Expanded to ------ ------ ------------ bbc chkbit; bno bbs chkbit; bo cmpibe cmpije cmpi; be cmpibg cmpijg cmpi; bg cmpibge cmpijge cmpi; bge cmpibl cmpijl cmpi; bl cmpible cmpijle cmpi; ble cmpibno cmpijno cmpi; bno cmpibne cmpijne cmpi; bne cmpibo cmpijo cmpi; bo cmpobe cmpoje cmpo; be cmpobg cmpojg cmpo; bg cmpobge cmpojge cmpo; bge cmpobl cmpojl cmpo; bl cmpoble cmpojle cmpo; ble cmpobne cmpojne cmpo; bne |