Component Reference

Chapter 4. Component Reference

Boolean AND Gate
Boolean NAND Gate
Clock Generator

Boolean Gates

Boolean AND Gate

Description

This component is a logic AND gate. The output is high if all inputs are high. The output is low if one or more inputs are low.

Features

  • User definable input count (2-26 inputs).

  • All inputs and the output are freely negatable.

  • The component supports a user definable reset state. The output adopts this state during the reset cycle and keeps this state until the first simulation cycle is finished. The default reset state is false.

  • The component is rotatable.

  • Use the component popup menu to add a new or remove a input (Currently you can only remove the last input which has to be unconnected).

View

Truth Table

Input AInput B Output
LowLow Low
LowHigh Low
HighLow Low
HighHigh High

Location

Boolean -> Gates -> AND

Boolean NAND Gate

Description

This component is a logic NAND gate. The output is low if all inputs are high. The output is high if one or more inputs are low.

Features

  • User definable input count (2-26 inputs).

  • All inputs and the output are freely negatable.

  • The component supports a user definable reset state. The output adopts this state during the reset cycle and keeps this state until the first simulation cycle is finished. The default reset state is false.

  • The component is rotatable.

  • Use the component popup menu to add a new or remove a input (Currently you can only remove the last input which has to be unconnected).

View

Truth Table

Input AInput B Output
LowLow High
LowHigh High
HighLow High
HighHigh Low

Location

Boolean -> Gates -> NAND

Clock Generator

Description

This component is a Clock Generator with a free definable timing. The Clock Generator supports a start delay, a high level duration and a low level duration.

The time can be given in a time unit (ps,ns,µs,ms,s) or in simulation cycles (ticks). Press the left mouse button in the input line and see the available manipulation options. The input of new delay time with one of the available unit works well. Or use the mouse wheel for changing the value in a 1-2-5 scheme.

Features

  • The output is negatable.

  • The clock generator supports a defineable start delay.

  • The high level duration and the low level duration are independent definable.

  • If the high level or the low level duration is shorter than a simulation cycle the duration is extended to one simulation cycle.

  • The component is rotatable.

View

Location

Boolean -> Gates -> Clock Generator

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