Boolean AND Gate |
Boolean NAND Gate |
Clock Generator |
This component is a logic AND gate. The output is high if all inputs are high. The output is low if one or more inputs are low.
The component supports a user definable reset state. The output adopts this state during the reset cycle and keeps this state until the first simulation cycle is finished. The default reset state is false.
Use the component popup menu to add a new or remove a input (Currently you can only remove the last input which has to be unconnected).
This component is a logic NAND gate. The output is low if all inputs are high. The output is high if one or more inputs are low.
The component supports a user definable reset state. The output adopts this state during the reset cycle and keeps this state until the first simulation cycle is finished. The default reset state is false.
Use the component popup menu to add a new or remove a input (Currently you can only remove the last input which has to be unconnected).
This component is a Clock Generator with a free definable timing. The Clock Generator supports a start delay, a high level duration and a low level duration.
The time can be given in a time unit (ps,ns,µs,ms,s) or in simulation cycles (ticks). Press the left mouse button in the input line and see the available manipulation options. The input of new delay time with one of the available unit works well. Or use the mouse wheel for changing the value in a 1-2-5 scheme.